1. Technical Field
The present invention relates to a circuit describing a low voltage differential signaling driver architecture, particularly to a low voltage differential signaling driver architecture using transmission gates as current switches.
2. Description of the Related Art
Recent developments in the areas of telecommunications, data communications, personal computers market etc., has seen an increasing demand for high speed processing is continuously increasing. In order to transmit data effectively and efficiently at high speeds and at the same time ensure consumption of low power, Low Voltage Differential Signaling (hereinafter referred to as LVDS) driver circuits have evolved, catering to a plethora of applications. LVDS drivers are used, for example, in Scalable Coherent Signal interfaces (SCI) for transmitting data via point-point connections quickly and efficiently. With SCI interfaces, much higher speeds are achieved than with conventional data buses. Typically, a LVDS driver can operate with data rates of 500 Mb/s per second per signal pair and above being fully compatible with IEEE Std 1596.3-1996 for general-purpose links and IEEE 1394a interfaces.
FIG. 1 shows the architecture of a conventional LVDS (Low Voltage Differential Signal) driver architecture. The LVDS driver may be used in the data transmission of a LCD (Liquid Crystal Display). Because the voltage amplitude of the LVDS driver is smaller, the transmission speed may be faster. As shown in FIG. 1, the LVDS driver architecture 11 includes current sources CS1 and CS2, a switch unit 111, a common mode feedback unit 112 and a transistor MNR (common mode resistance unit). The currents of the current sources CS1 and CS2 are defined as I1 and I2. The switch unit 111 includes transistors MP1, MP2, MN1 and MN2. The transistors MP1, MP2, MN1 and MN2 of the switch unit 111, which are controlled by input signals IN and INB, determine the current direction of the output current Iout. That is, when the input signal IN is a high logic level and the input signal INB is a low logic level, the transistors MP2 and MN1 are ON and the transistors MP1 and MN2 are OFF. Thus, the output current Iout is positive. At this time, a resistor R1 of a receiver 12 receives the positive signal. When the input signal IN is the low logic level and the input signal INB is the high logic level, the transistors MP2 and MN1 are OFF and the transistors MP1 and MN2 are ON. Thus, the output current Iout is negative. At this time, the resistor R1 of the receiver 12 receives the negative signal. The receiver 12 includes the resistor R1 and a receiving unit 121.
In addition, the LVDS driver 11 further includes a common mode feedback (CMFB) unit 112 and the transistor MNR, which serves as a resistor to adjust the common mode voltage for transmission data. If the resistance value of the transistor MNR is Rc, then the voltage Va at the node a is: Va=I*Rc, wherein I is the difference of the current between the current source CS1 and the current source CS2, i.e., I=I1−I2. If the resistance value of the impedance matched resistor R1 of the receiver 12 is 100 Ohms(Ω), then the common mode voltage for transmission data is (Va+I1*100/2). In the architecture of FIG. 1, the current source CS1 plays an important role in the PSRR (Power Supply Rejection Ration). The ideal current source CS1 has a best PSRR. In other words, because the current source CS1 has the non-ideal characteristic, the power noise influences the common mode level for transmission data. The influence can be induced by the parasitic capacitance and the channel length modulation (Vds*λ). From the viewpoint of the influence of the channel length modulation, the current variation ΔI1 of the current source CS1 is in direct proportion to the power voltage variation (noise) ΔVDD, i.e., ΔI1=ΔVDD*K1.
Similarly, owing to the influence of the channel length modulation, ΔVa is in direct proportion to ΔI1, so ΔVa is also in direct proportion to ΔVDD, i.e., ΔVa=ΔVDD*K2. Thus, the voltage Va at the node a is influenced by the power voltage VDD such that the common mode level is also influenced by the power voltage VDD.
Of course, some prior arts may be adopted to improve the characteristic of the current source CS1. For example, a cascode current source or a current source with a longer channel may be used. However, the voltage headroom of the cascode current source is restricted in the deep submicron technology, while using the current source with a longer channel requires a larger chip area and includes some limitations. Of course, the common mode feedback unit can correct the influence of the power noise, but the correction cannot be made in real time and is restricted by the bandwidth of the common mode feedback unit.